1. Field of the Invention
The present invention relates to a modulator, and more particularly to a digital modulator used in radio communications and so forth. Furthermore, the present invention relates to a technology that is effective for application to a Hybrid Phase Shift Keying (HPSK) modulator used with the W-CDMA (Wideband—Code Division Multiple Access) method.
2. Description of the Related Art
In a communication system that uses the W-CDMA method, in reception a control channel is inserted into a transmit channel by time division. In transmission, on the other hand, the HPSK modulation method is used. With this HPSK modulation method, orthogonal components of spread data of multiple channels are converted to vector values, and these are further rotated using a scrambling code. When the HPSK modulation method is used for normal transmission (single mode), two channels—a transmit channel and a control channel—are provided, and multimode operation is established if transmit channels are further superimposed in this state.
Concrete examples of multimode operation include a case where image data is sent at the same time as voice data, and a case where mail data is sent at the same time as voice data. As the amount of data transmitted differs for voice data and image data, voice data is transmitted at low speed and mail data at high speed. The transmission data rates are in the range from 15 kbps to 960 kbps, and are variable. The chip rate (spreading code rate) is 3.84 MHz, and one data is spread using a ratio of 4 chips to 256 chips.
In a communication system using this kind of HPSK modulation method, reception becomes difficult on the receiving side at high speeds, and therefore transmission power is varied according to the transmission data rate of the transmitting side. That is to say, control is performed so that the speed of the transmission data rate and the magnitude of the transmission power are made proportional, and transmission power is increased as the transmission data rate becomes faster, enabling reception to be performed easily during high-speed communication. This function was previously relegated to the high-frequency region (RF region), but when the W-CDMA method is used this function tends to be used in the baseband region in order to handle multimode operation.
Transmission gain that makes transmission power variable is called β. In the baseband section, since a voltage is output, the transmission gain β value is made proportional to the transmission data rate, and is set in the range 0 to 15 (4 bits).
A single-mode HPSK modulator is disclosed in Unexamined Japanese Patent Publication No. 2001-339365. as shown in FIG. 12, this HPSK modulator is equipped with multipliers 11 and 17, a complex arithmetic section 101 composed of multipliers 21, 27, and 37, raised COS filters 41 through 44, envelope generators 91 and 92, multipliers 81 through 84, and adders 71 and 72.
Multiplier 11 multiplies transmit data 1 of dedicated physical data channel DPDCH1 by a spreading code. Multiplier 17 multiplies control data 7 of dedicated physical control channel DPCCH by a spreading code. Complex arithmetic section 101 performs complex arithmetic between the outputs of multipliers 11 and 17 and a scrambling code, and generates real part data and imaginary part data for each channel. Raised COS filters 41 through 44 band-limit the output data of each channel from complex arithmetic section 101. Multipliers 81 through 84 multiply the output data of raised COS filters 41 through 44 by a gain factor. Adder 71 adds together the real part data output from multipliers 81 and 82, and adder 72 adds together the imaginary part data output from multipliers 82 and 84.
To be more specific, multipliers 11 and 17 each comprise an exclusive-OR circuit. Multipliers 21, 27, and 37 each comprise an exclusive-OR circuit or two exclusive-NOR circuits. Raised COS filters 41 through 44 each comprise a 1-bit-input FIR filter (Finite Impulse Response Filter).
Multiplier 11 multiplies transmit data 1 input via dedicated physical data channel DPDCH1 by a transmit data spreading code Cd1, and outputs output data I (=Cd1×DPDCH1) to multiplier 21. Here, transmit data 1 is 1-bit data with a data rate of 15 kbps to 960 kbps, for example, and transmit data spreading code Cd1 is 1-bit data with a chip rate of 3.84 MHz, for example. Therefore, multiplier 11 output data I is 1-bit data that varies on a chip-by-chip basis.
Multiplier 17 multiplies control data 7 input via dedicated physical control channel DPCCH by a control data spreading code Cc, and outputs output data Q (=Cc×DPCCH) to multiplier 37. Here, control data 7 is 1-bit data with a data rate of 15 kbps, for example, and control data spreading code Cc is 1-bit data with a chip rate of 3.84 MHz, for example. Therefore, multiplier 17 output data Q is 1-bit data that varies on a chip-by-chip basis.
Multiplier 21 performs complex arithmetic in which output data I from multiplier 11 is multiplied by a scrambling code Sn, and outputs 1-bit complex data comprising real part data Ii1 (=SIn×I) and imaginary part data Iq1 (=SQn×Q). Here, scrambling code Sn comprises complex data with a chip rate of 3.84 MHz, each of 1 bit, for example. SIn is scrambling code Sn real number data, and SQn is scrambling code Sn imaginary number data.
Multiplier 27 has, as input, output data jQ from multiplier 37 in which output data Q from multiplier 17 has been multiplied by an imaginary number j. Multiplier 27 performs complex arithmetic in which output data jQ is multiplied by a scrambling code Sn, and outputs 1-bit complex number data comprising real part data Qi1 (=SIn×Q) and imaginary part data Qq1 (=−SQn×I).
Raised COS filter 41 outputs multi-bit data Ii2 in which multiplier 21 output data Ii1 has been band-limited. Raised COS filter 42 outputs multi-bit data Iq2 in which multiplier 21 output data Iq1 has been band-limited. Raised COS filter 43 outputs multi-bit data Qi2 in which multiplier 27 output data Qi1 has been band-limited. Raised COS filter 44 outputs multi-bit data Qq2 in which multiplier 27 output data Qq1 has been band-limited. Here, 10-bit impulse response FIR filters are used for raised COS filters 41 through 44, and each of output data Ii2, Iq2, Qi2, and Qq2 is 10-bit data.
Envelope generator 91 outputs gain factor βd1′ for which smooth envelope control is performed when gain factor βd1 is changed. Envelope generator 92 outputs gain factor βc′ for which smooth envelope control is performed when gain factor βc is changed. Here, βd1=βd1′ and βc=βc′.
Multiplier 81 performs multiplication of output data Ii2 from raised COS filter 41 and gain factor βd1, generates multi-bit data Ii3, and outputs this to adder 71. Multiplier 82 performs multiplication of output data Iq2 from raised COS filter 42 and gain factor d1, generates multi-bit data Iq3, and outputs this to adder 72.
Multiplier 83 performs multiplication of output data Qi2 from raised COS filter 43 and gain factor βc, generates multi-bit data Qi3, and outputs this to adder 71. Multiplier 84 performs multiplication of output data Qq2 from raised COS filter 44 and gain factor βc, generates multi-bit data Qq3, and outputs this to adder 72.
Adder 71 generates output data Iout (=Ii3+Qi3) comprising multi-bit data in which output data Ii3 from data channel multiplier 81 and output data Qi3 from control channel multiplier 83 have been added, and outputs this output data Iout. Adder 72 generates output data Qout (=Iq3+Qq3) comprising multi-bit data in which output data Iq3 from data channel multiplier 82 and output data Qq3 from control channel multiplier 84 have been added, and outputs this output data Qout. Output data Iout output from adder 71 and output data Qout output from adder 72 undergo digital-analog conversion in next-stage D/A converters, and are sent to the high-frequency area.
However, in the above-described HPSK modulator, consideration has not been given to the fact that, since outputs from raised COS filters 41 through 44 and gain factors βd1 and βc are multiplied, multi-bit multipliers operating at a rate of n times 3.84 MHz are necessary, increasing circuit scale and power consumption.